HD6432351 datasheet(132/1025 Pages) RENESAS

132 / 1025 page

Section 5 Interrupt Controller

Rev. 3.00 Sep 15, 2006 page 98 of 988

REJ09B0330-0300

5.2.5

IRQ Status Register (ISR)

IRQ7F

R/(W)*

IRQ6F

R/(W)*

IRQ5F

R/(W)*

IRQ4F

R/(W)*

IRQ3F

R/(W)*

IRQ0F

R/(W)*

IRQ2F

R/(W)*

IRQ1F

R/(W)*

Bit

Initial value

R/W

Note: * Only 0 can be written, to clear the flag.

ISR is an 8-bit readable/writable register that indicates the status of IRQ7 to IRQ0 interrupt

requests.

ISR is initialized to H'00 by a reset and in hardware standby mode.

Bits 7 to 0—IRQ7 to IRQ0 flags (IRQ7F to IRQ0F): These bits indicate the status of IRQ7 to

IRQ0 interrupt requests.

Bit n

IRQnF

Description

[Clearing conditions] (Initial value)

• Cleared by reading IRQnF flag when IRQnF = 1, then writing 0 to IRQnF flag

• When interrupt exception handling is executed when low-level detection is set

(IRQnSCB = IRQnSCA = 0) and

IRQn input is high

• When IRQn interrupt exception handling is executed when falling, rising, or both-

edge detection is set (IRQnSCB = 1 or IRQnSCA = 1)

• When the DTC is activated by an IRQn interrupt, and the DISEL bit in MRB of the

DTC is cleared to 0

[Setting conditions]

• When IRQn input goes low when low-level detection is set (IRQnSCB = IRQnSCA

= 0)

• When a falling edge occurs in IRQn input when falling edge detection is set

(IRQnSCB = 0, IRQnSCA = 1)

• When a rising edge occurs in IRQn input when rising edge detection is set

(IRQnSCB = 1, IRQnSCA = 0)

• When a falling or rising edge occurs in IRQn input when both-edge detection is set

(IRQnSCB = IRQnSCA = 1)

Note: n = 7 to 0

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