HD6432351 datasheet(159/1025 Pages) RENESAS

159 / 1025 page

Section 6 Bus Controller

Rev. 3.00 Sep 15, 2006 page 125 of 988

REJ09B0330-0300

Name

Symbol

I/O

Function

Chip select 7

CS7

Output

Strobe signal indicating that area 7 is

selected.

Upper column address strobe

CAS

Output

2-CAS DRAM upper column address

strobe signal.

Lower column strobe

LCAS

Output

DRAM lower column address strobe signal.

Wait

WAIT

Input

Wait request signal when accessing

external 3-state access space.

Bus request

BREQ

Input

Request signal that releases bus to

external device.

Bus request acknowledge

BACK

Output

Acknowledge signal indicating that bus has

been released.

Bus request output

BREQO

Output

External bus request signal used when

internal bus master accesses external

space when external bus is released.

6.1.4

Table 6.2 summarizes the registers of the bus controller.

Table 6.2

Bus Controller Registers

Initial Value

Name

Abbreviation

R/W

Power-On

Reset

Manual

Reset

Address*

Bus width control register

ABWCR

R/W

H'FF/H'00*

2 Retained

H'FED0

Access state control register

ASTCR

R/W

H'FF

Retained

H'FED1

Wait control register H

WCRH

R/W

H'FF

Retained

H'FED2

Wait control register L

WCRL

R/W

H'FF

Retained

H'FED3

Bus control register H

BCRH

R/W

H'D0

Retained

H'FED4

Bus control register L

BCRL

R/W

H'3C

Retained

H'FED5

Memory control register

MCR

R/W

H'00

Retained

H'FED6

DRAM control register

DRAMCR

R/W

H'00

Retained

H'FED7

Refresh timer/counter

RTCNT

R/W

H'00

Retained

H'FED8

Refresh time constant register

RTCOR

R/W

H'FF

Retained

H'FED9

Notes: 1. Lower 16 bits of the address.

2. Determined by the MCU operating mode.

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