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HD6432351 Datasheet(PDF) 291 Page - Renesas Technology Corp |
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HD6432351 Datasheet(HTML) 291 Page - Renesas Technology Corp |
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291 / 1025 page ![]() Section 7 DMA Controller (DMAC) Rev. 3.00 Sep 15, 2006 page 257 of 988 REJ09B0330-0300 Acquire bus ETCRAL = ETCRAL –1 Transfer request? ETCRAL = H'00 Release bus BLKDIR = 0 ETCRAL = ETCRAH ETCRB = ETCRB –1 ETCRB = H'0000 Start (DTE = DTME = 1) Read address specified by MARA MARA = MARA + SAIDE · (–1)SAID · 2DTSZ Write to address specified by MARB MARB = MARB + DAIDE · (–1)DAID · 2DTSZ MARB = MARB – DAIDE · (–1)DAID · 2DTSZ · ETCRAH MARA = MARA – SAIDE · (–1)SAID · 2DTSZ · ETCRAH No Yes No Yes No Yes No Yes Clear DTE bit to 0 to end transfer Figure 7.15 Operation Flow in Block Transfer Mode |
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