H8SX1663 datasheet(175/1158 Pages) RENESAS

175 / 1158 page

Section 5 Interrupt Controller

Rev.1.00 Jun. 07, 2006 Page 123 of 1102

REJ09B0294-0100

Select signal

DTCER

DMRSR_0 to DMRSR_3

Select signal

IRQ

interrupt

On-chip

peripheral

module

Interrupt controller

Clear signal

Control signal

DMAC activation request signal

Clear signal

DTC/CPU

select

circuit

DMAC

select

circuit

DTC control

circuit

Priority

determination

DTC

DMAC

CPU

Interrupt request

Clear signal

Interrupt request

clear signal

Interrupt request clear signal

Interrupt request

DTC activation request

vector number

CPU interrupt request

vector number

Clear signal

I, I2 to I0

Figure 5.6 Block Diagram of DTC, DMAC, and Interrupt Controller

(1)

Selection of Interrupt Sources

The activation source for each DMAC channel is selected by DMRSR. The selected activation

source is input to the DMAC through the select circuit. When transfer by an on-chip module

interrupt is enabled (DTF1 = 1, DTF0 = 0, and DTE = 1 in DMDR) and the DTA bit in DMDR is

set to 1, the interrupt source selected for the DMAC activation source is controlled by the DMAC

and cannot be used as a DTC activation source or CPU interrupt source.

Interrupt sources that are not controlled by the DMAC are set for DTC activation sources or CPU

interrupt sources by the DTCE bit in DTCERA to DTCERH of the DTC.

Specifying the DISEL bit in MRB of the DTC generates an interrupt request to the CPU by

clearing the DTCE bit to 0 after the individual DTC data transfer.

Note that when the DTC performs a predetermined number of data transfers and the transfer

counter indicates 0, an interrupt request is made to the CPU by clearing the DTCE bit to 0 after the

DTC data transfer.

When the same interrupt source is set as both the DTC and DMAC activation source and CPU

interrupt source, the DTC and DMAC must be given priority over the CPU. If the IPSETE bit in

CPUPCR is set to 1, the priority is determined according to the IPR setting. Therefore, the CPUP

setting or the IPR setting corresponding to the interrupt source must be set to lower than or equal

to the DTCP and DMAP setting. If the CPU is given priority over the DTC or DMAC, the DTC or

DMAC may not be activated, and the data transfer may not be performed.

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