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H8SX1663 Datasheet(PDF) 261 Page - Renesas Technology Corp |
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H8SX1663 Datasheet(HTML) 261 Page - Renesas Technology Corp |
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261 / 1158 page  Section 6 Bus Controller (BSC) Rev.1.00 Jun. 07, 2006 Page 209 of 1102 REJ09B0294-0100 6.7.5 Wait Control The bus cycle can be extended for the byte control SRAM interface by inserting wait cycles (Tw) in the same way as the basic bus interface. (1) Program Wait Insertion From 0 to 7 wait cycles can be inserted automatically between T2 cycle and T3 cycle for the 3- state access space in area units, according to the settings in WTCRA and WTCRB. (2) Pin Wait Insertion For 3-state access space, when the WAITE bit in BCR1 is set to 1, the corresponding DDR bit is cleared to 0, and the ICR bit is set to 1, wait input by means of the WAIT pin is enabled. For details on DDR and ICR, refer to section 9, I/O Ports. Figure 6.27 shows an example of wait cycle insertion timing. |
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