H8SX1663 datasheet(284/1158 Pages) RENESAS

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H8SX1663 Datasheet(PDF) 284 Page - Renesas Technology Corp

Part #	H8SX1663

Description	Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

PDF	1158 Pages

Scroll/Zoom	100%

Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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284 / 1158 page

Section 6 Bus Controller (BSC)

Rev.1.00 Jun. 07, 2006 Page 232 of 1102

REJ09B0294-0100

6.10.7

Controlling Row Address Output Cycle

The

RAS signal is driven low at the start of the Tr cycle by setting the RAST bit to 1. The row

address hold time to the falling edge of the

RAS signal and the DRAM read access time are

changed. Set the bit according to the DRAM to be used and the frequency of this LSI so that

required performance can be obtained.

Figure 6.40 shows a timing example when the

RAS signal is driven low at the start of the Tr cycle.

Address bus

Row address

Column address

RAS

LUCAS

LLCAS

OE (RD)

Data bus

High

Read

Write

Data bus

RD/

Figure 6.40 Access Timing Example of

RAS Signal Driven Low at Start of Tr Cycle

(CAST = 0)

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