H8SXSLASH1525R datasheet(13/826 Pages) RENESAS

13 / 826 page

Rev. 1.00 Mar. 06, 2006 Page xiii of xxxviii

7.5

DMA Transfer End ............................................................................................................ 196

7.6

Relationship among DMAC and Other Bus Masters ......................................................... 198

7.6.1

CPU Priority Control Function Over DMAC ....................................................... 198

7.6.2

Bus Arbitration among DMAC and Other Bus Masters ....................................... 199

7.7

Interrupt Sources................................................................................................................ 200

7.8

Notes on Usage ..................................................................................................................203

Section 8 I/O Ports .............................................................................................205

8.1

Register Descriptions ......................................................................................................... 210

8.1.1

Data Direction Register (PnDDR) (n = 1 to 3, 6, A, D, H, J, and K).................... 212

8.1.2

Data Register (PnDR) (n = 1 to 3, 6, A, D, H, J, and K)....................................... 212

8.1.3

Port Register (PORTn) (n = 1 to 6, A, D, H, J, and K) ......................................... 213

8.1.4

Input Buffer Control Register (PnICR) (n = 1 to 6, A, D, H, J, and K) ................ 213

8.1.5

Pull-Up MOS Control Register (PnPCR) (n = D, H, J, and K)............................. 214

8.1.6

Open-Drain Control Register (PnODR) (n = 2) .................................................... 215

8.1.7

Port H Realtime Input Data Register (PHRTIDR)................................................ 215

8.2

Output Buffer Control........................................................................................................ 216

8.2.1

Port 1..................................................................................................................... 216

8.2.2

Port 2..................................................................................................................... 219

8.2.3

Port 3..................................................................................................................... 221

8.2.4

Port 6..................................................................................................................... 225

8.2.5

Port A.................................................................................................................... 227

8.2.6

Port D.................................................................................................................... 230

8.2.7

Port H.................................................................................................................... 233

8.2.8

Port J ..................................................................................................................... 233

8.2.9

Port K.................................................................................................................... 236

8.3

Port Function Controller .................................................................................................... 243

8.3.1

Port Function Control Register 9 (PFCR9)........................................................... 243

8.3.2

Port Function Control Register A (PFCRA) ......................................................... 245

8.3.3

Port Function Control Register B (PFCRB).......................................................... 247

8.4

Usage Notes ....................................................................................................................... 249

8.4.1

Notes on Input Buffer Control Register (ICR) Setting ......................................... 249

8.4.2

Notes on Port Function Control Register (PFCR) Settings................................... 249

Section 9 16-Bit Timer Pulse Unit (TPU) .........................................................251

9.1

Features.............................................................................................................................. 251

9.2

Input/Output Pins ...............................................................................................................258

9.3

Register Descriptions ......................................................................................................... 260

9.3.1

Timer Control Register (TCR).............................................................................. 265

9.3.2

Timer Mode Register (TMDR) ............................................................................. 270

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