H8SXSLASH1653 datasheet(13/1018 Pages) RENESAS

13 / 1018 page

Rev.1.00 Sep. 08, 2005 Page xiii of xlviiil

6.7.5

Wait Control ......................................................................................................... 189

6.7.6

Read Strobe (

RD).................................................................................................. 191

6.7.7

Extension of Chip Select (

CS) Assertion Period................................................... 191

6.7.8

DACK Signal Output Timing ............................................................................... 191

6.8

Burst ROM Interface.......................................................................................................... 193

6.8.1

Burst ROM Space Setting..................................................................................... 193

6.8.2

Data Bus................................................................................................................ 193

6.8.3

I/O Pins Used for Burst ROM Interface................................................................ 194

6.8.4

Basic Timing......................................................................................................... 195

6.8.5

Wait Control ......................................................................................................... 197

6.8.6

Read Strobe (

RD) Timing..................................................................................... 197

6.8.7

Extension of Chip Select (

CS) Assertion Period................................................... 197

6.9

Address/Data Multiplexed I/O Interface ............................................................................ 198

6.9.1

Address/Data Multiplexed I/O Space Setting ....................................................... 198

6.9.2

Address/Data Multiplex ........................................................................................ 198

6.9.3

Data Bus................................................................................................................ 198

6.9.4

I/O Pins Used for Address/Data Multiplexed I/O Interface .................................. 199

6.9.5

Basic Timing......................................................................................................... 200

6.9.6

Address Cycle Control.......................................................................................... 202

6.9.7

Wait Control ......................................................................................................... 203

6.9.8

Read Strobe (

RD) Timing.................................................................................... 203

6.9.9

Extension of Chip Select (

CS) Assertion Period................................................... 205

6.9.10

DACK Signal Output Timing ............................................................................... 207

6.10

Idle Cycle........................................................................................................................... 208

6.10.1 Operation .............................................................................................................. 208

6.10.2 Pin States in Idle Cycle ......................................................................................... 217

6.11

Bus Release........................................................................................................................ 218

6.11.1 Operation .............................................................................................................. 218

6.11.2 Pin States in External Bus Released State............................................................. 219

6.11.3 Transition Timing ................................................................................................. 220

6.12

Internal Bus........................................................................................................................ 221

6.12.1 Access to Internal Address Space ......................................................................... 221

6.13

Write Data Buffer Function ............................................................................................... 222

6.13.1 Write Data Buffer Function for External Data Bus............................................... 222

6.13.2 Write Data Buffer Function for Peripheral Modules ............................................ 223

6.14

Bus Arbitration................................................................................................................... 224

6.14.1 Operation .............................................................................................................. 224

6.14.2 Bus Transfer Timing ............................................................................................. 225

6.15

Bus Controller Operation in Reset ..................................................................................... 227

6.16

Usage Notes ....................................................................................................................... 227

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