SH7065 datasheet(13/941 Pages) RENESAS

13 / 941 page

Rev. 5.00 Sep 11, 2006 page xiii of xxii

7.4

Examples of Use ............................................................................................................... 214

7.5

Usage Notes ...................................................................................................................... 217

7.5.1

Changes to UBC Register Settings....................................................................... 217

7.5.2

Repeat Condition Breaks ..................................................................................... 217

Section 8 Bus State Controller (BSC) ........................................................................... 219

8.1

Overview........................................................................................................................... 219

8.1.1

Features................................................................................................................ 219

8.1.2

Block Diagram ..................................................................................................... 221

8.1.3

Pin Configuration................................................................................................. 222

8.1.4

8.1.5

Address Format.................................................................................................... 225

8.2

Register Descriptions ........................................................................................................ 228

8.2.1

Bus Control Register (BCR) ................................................................................ 228

8.2.2

Area Control Registers 1 (ACR1_0 to ACR1_5) ................................................. 229

8.2.3

Wait Control Registers (WCR_0 to WCR_3) ...................................................... 233

8.2.4

DRAM Control Register 1 (DCR1) ..................................................................... 235

8.2.5

DRAM Control Register 2 (DCR2) ..................................................................... 237

8.2.6

DRAM Control Register 3 (DCR3) ..................................................................... 240

8.2.7

Refresh Timer Control/Status Register (RTCSR) ................................................ 242

8.2.8

Refresh Timer Counter (RTCNT) ........................................................................ 245

8.2.9

Refresh Time Constant Register (RTCOR).......................................................... 246

8.2.10 Refresh Count Register (RFCR)........................................................................... 247

8.3

Operation........................................................................................................................... 248

8.3.1

Endian/Access Size and Data Alignment ............................................................. 248

8.3.2

Areas .................................................................................................................... 254

8.3.3

Normal Space Access........................................................................................... 255

8.3.4

DRAM Interface .................................................................................................. 267

8.3.5

Multiplexed Address/Data I/O Interface .............................................................. 286

8.3.6

Waits between Access Cycles .............................................................................. 291

8.3.7

Bus Arbitration..................................................................................................... 293

8.4

Number of Access Cycles (SH7065A).............................................................................. 295

8.5

Usage Notes ...................................................................................................................... 304

Section 9 Direct Memory Access Controller (DMAC) ............................................ 305

9.1

Overview........................................................................................................................... 305

9.1.1

Features................................................................................................................ 305

9.1.2

Block Diagram ..................................................................................................... 307

9.1.3

Pin Configuration................................................................................................. 308

9.1.4

9.2

Register Descriptions ........................................................................................................ 311

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