HD6433044F datasheet(9/905 Pages) RENESAS

9 / 905 page

Rev. 7.00 Sep 21, 2005 page ix of xxiv

Item

Page

Revision (See Manual for Details)

19.5.6 Erasing

Flowchart and

Sample Program

Prewrite Flowchart

Figure 19.11

Prewrite Flowchart

611

Figure amended

End of prewrite

≥ N?

n + 1

Double

the programming

time (x

× 2 → x)

→ n

Write H'00 to flash memory

(flash memory latches

write address and write data)

Enable watchdog timer*2

Select program mode

(set P bit to 1 in FLMCR)

Wait (x) µs

Clear P bit

Disable watchdog timer

Wait (tVS1) µs

Prewrite verify*3

(read data = H'00?)

Last address?

No good

Yes

Programming ends

Programming error

Yes

Clear

bit

Clear erase block register

(clear bit of block to be erased to 0)

Clear erase block register

(clear bit of block to be erased to 0)

Clear VPPE bit

Notes: 1. Use a byte transfer instruction.

2. Set the watchdog timer overflow

interval by setting CKS2 = 0,

CKS1 = 0 and CKS0 = 1.

3. In prewrite-verify mode P, E, PV,

and EV are all cleared to 0 and

12 V is applied to VPP. Use a

byte transfer instruction.

4. tVS1: 4

µs

5 to 10

µs

6 (set N so that total

programming time does not

exceed 1 ms)

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