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SH7205 Datasheet(PDF) 30 Page - Renesas Technology Corp |
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SH7205 Datasheet(HTML) 30 Page - Renesas Technology Corp |
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30 / 1904 page ![]() Rev. 1.00 Mar. 25, 2008 Page xxx of xxxii 28.2.18 Port K Data Register L (PKDRL) ....................................................................... 1533 28.2.19 Port K Port Register L (PKPRL) ........................................................................ 1534 28.3 Usage Notes ..................................................................................................................... 1535 Section 29 On-Chip RAM ............................................................................... 1537 29.1 Features............................................................................................................................ 1537 29.2 Usage Notes ..................................................................................................................... 1540 29.2.1 Page Conflict ...................................................................................................... 1540 29.2.2 RAME Bit and RAMWE Bit .............................................................................. 1540 Section 30 Power-Down Modes...................................................................... 1541 30.1 Power-Down Modes ........................................................................................................ 1541 30.2 Register Descriptions ....................................................................................................... 1543 30.2.1 Standby Control Register 1 (STBCR1)............................................................... 1544 30.2.2 Standby Control Register 2 (STBCR2)............................................................... 1545 30.2.3 Standby Control Register 3 (STBCR3)............................................................... 1546 30.2.4 Standby Control Register 4 (STBCR4)............................................................... 1548 30.2.5 Standby Control Register 5 (STBCR5)............................................................... 1549 30.2.6 Standby Control Register 6 (STBCR6)............................................................... 1550 30.2.7 Standby Control Register 7 (STBCR7)............................................................... 1552 30.2.8 System Control Register 1 (SYSCR1) ................................................................ 1553 30.2.9 System Control Register 2 (SYSCR2) ................................................................ 1554 30.2.10 System Control Register 3 (SYSCR3) ................................................................ 1556 30.2.11 System Control Register 4 (SYSCR4) ................................................................ 1556 30.2.12 System Control Register 5 (SYSCR5) ................................................................ 1556 30.2.13 System Control Register 6 (SYSCR6) ................................................................ 1556 30.2.14 System Control Register 7 (SYSCR7) ................................................................ 1557 30.2.15 System Control Register 8 (SYSCR8) ................................................................ 1558 30.2.16 System Control Register 9 (SYSCR9) ................................................................ 1559 30.2.17 System Control Register 10 (SYSCR10) ............................................................ 1559 30.2.18 System Control Register 11 (SYSCR11) ............................................................ 1559 30.2.19 System Control Register 12 (SYSCR12) ............................................................ 1559 30.2.20 Software Reset Control Register (SWRSTCR) .................................................. 1560 30.2.21 High-Impedance Control Register (HIZCR)....................................................... 1562 30.2.22 CPU0/CPU1 Mode Status Registers (C0MSR, C1MSR) ................................... 1563 30.2.23 Data Retention On-Chip RAM Area Specification Register (RRAMKP) .......... 1564 30.2.24 Deep Standby Control Register (DSCTR) .......................................................... 1565 30.2.25 Deep Standby Cancel Source Select Register (DSSSR) ..................................... 1566 30.2.26 Deep Standby Cancel Source Flag Register (DSFR) .......................................... 1568 30.3 Operation ......................................................................................................................... 1570 |
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