HD6433636SW datasheet(373/418 Pages) RENESAS

373 / 418 page

359

TMG—Timer mode register G

H'BC

Timer G

Bit

Initial value

Read/Write

OVFH

R/(W)

OVFL

R/(W)

OVIE

R/W

IIEGS

R/W

CCLR1

R/W

CKS0

R/W

CCLR0

R/W

CKS1

R/W

Timer overflow flag H

[Clearing condition]

After reading OVFH = 1, cleared by writing 0 to OVFH

[Setting condition]

When the value of TCG overflows from H'FF to H'00

Note:

Only a write of 0 for flag clearing is possible.

Timer overflow interrupt enable

Timer overflow flag L

[Clearing condition]

After reading OVFL = 1, cleared by writing 0 to OVFL

[Setting condition]

When the value of TCG overflows from H'FF to H'00

TCG overflow interrupt disabled

TCG overflow interrupt enabled

Input capture interrupt edge select

Interrupts are requested at the rising edge of the input capture signal

Interrupts are requested at the falling edge of the input capture signal

Clock select

Internal clock:

ø/64

ø/32

ø/2

ø /2

Counter clear

TCG is not cleared

TCG is cleared at the falling edge of the input capture signal

TCG is cleared at the rising edge of the input capture signal

TCG is cleared at both edges of the input capture signal

HD6433636SW Datasheet(PDF) 373 Page - Renesas Technology Corp

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