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HD6433636SW Datasheet(PDF) 83 Page - Renesas Technology Corp |
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HD6433636SW Datasheet(HTML) 83 Page - Renesas Technology Corp |
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83 / 418 page ![]() 69 Bits 7 to 0—Wakeup Interrupt Request Flags (IWPF7 to IWPF0) Bits 7 to 0: IWPF7 to IWPF0 Description 0 [Clearing conditions] (initial value) When IWPFn = 1, it is cleared by writing 0 to IWPFn. 1 [Setting conditions] IWPFn is set when pin WKP n is set to wakeup interrupt input, and a falling edge input is detected at the pin. (n = 7 to 0) 3.3.3 External Interrupts There are 13 external interrupts, WKP 0 to WKP7 and IRQ0 to IRQ4. Interrupts WKP 0 to WKP7: Interrupts WKP0 to WKP7 are requested by falling edge inputs at pins WKP 0 to WKP7. When these pins are designated as WKP0 to WKP7 pins in port mode register 5 (PMR5) and falling edge input is detected, the corresponding bit in the wakeup interrupt request register (IWPR) is set to 1, requesting an interrupt. Wakeup interrupt requests can be disabled by clearing the IENWP bit in IENR1 to 0. It is also possible to mask all interrupts by setting the CCR I bit to 1. When an interrupt exception handling request is received for interrupts WKP 0 to WKP7, the CCR I bit is set to 1. The vector number for interrupts WKP 0 to WKP7 is 9. Since all eight interrupts are assigned the same vector number, the interrupt source must be determined by the exception handling routine. Interrupts IRQ 0 to IRQ4: Interrupts IRQ0 to IRQ4 are requested by inputs into pins IRQ0 to IRQ4. These interrupts are detected by either rising edge sensing or falling edge sensing, depending on the settings of bits IEG0 to IEG4 in the edge select register (IEGR). When these pins are designated as pins IRQ 0 to IRQ4 in port mode registers 1 and 2 (PMR1 and PMR2) and the designated edge is input, the corresponding bit in IRR1 is set to 1, requesting an interrupt. Interrupts IRQ 0 to IRQ4 can be disabled by clearing bits IEN0 to IEN4 in IENR1 to 0. All interrupts can be masked by setting the I bit in CCR to 1. When IRQ 0 to IRQ4 interrupt exception handling is initiated, the I bit in CCR is set to 1. Vector numbers 4 to 8 are assigned to interrupts IRQ 0 to IRQ4. The order of priority is from IRQ0 (high) to IRQ 4 (low). Table 3.2 gives details. |
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