HD6433636SW datasheet(389/418 Pages) RENESAS

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IRR2—Interrupt request register 2

H'F7

System control

Bit

Initial value

Read/Write

IRRDT

R/W

IRRAD

R/W

—

IRRTG

R/W

IRRTFH

R/W

IRRTYC

IRRTFL

R/W

IRRTY

Direct transfer interrupt request flag

[Clearing condition]

When IRRDT = 1, it is cleared by writing 0

[Setting condition]

A SLEEP instruction is executed when DTON = 1 and a direct transfer is made

Note:

Only a write of 0 for flag clearing is possible.

A/D converter interrupt request flag

[Clearing condition]

When IRRAD = 1, it is cleared by writing 0

[Setting condition]

When A/D conversion is completed and ADSF is reset

Timer Y interrupt request flag

[Clearing condition]

When IRRTY is 1, it is cleared

by writing 0 to IRRTYC

[Setting condition]

When the timer Y counter value

overflows (from H'FFFF to H'0000)

Timer G interrupt request flag

[Clearing condition]

When IRRTG = 1, it is cleared by writing 0

[Setting condition]

When pin TMIG is set to TMIG input and the designated signal edge is detected

Timer FH interrupt request flag

[Clearing condition]

When IRRTFH = 1, it is cleared by writing 0

[Setting condition]

When counter FH matches output compare register

FH in 8-bit mode, or when 16-bit counter F (TCFL,

TCFH) matches 16-bit output compare register F

(OCRFL, OCRFH) in 16-bit mode

Timer FL interrupt request flag

[Clearing condition]

When IRRTFL = 1, it is cleared by writing 0

[Setting condition]

When TCFL matches in 8-bit mode

Timer Y interrupt request clear flag

This is a special bit for clearing the

IRRTY interrupt request flag. Writing

0 to this bit clears bit 1 (IRRTY) to 0.

Note that writing 0 to this bit does not

give the bit itself a value of 0.

This bit is always read as 1, and only

a write of 0 to this bit is valid.

Note: This bit is read-only. It is cleared

by writing 0 to bit 0 (IRRTYC).

HD6433636SW Datasheet(PDF) 389 Page - Renesas Technology Corp

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