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HD6433636SW Datasheet(PDF) 322 Page - Renesas Technology Corp |
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HD6433636SW Datasheet(HTML) 322 Page - Renesas Technology Corp |
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322 / 418 page  308 Notes: 1. A frequency between 1 MHz to 10 MHz is required when an external clock is input. 2. Selected with SA1 and SA0 of system clock control register 2 (SYSCR2). Table 14.3 Control Signal Timing (cont) V CC = 2.2 V to 5.5 V, AVCC = 2.2 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = –20 to +75°C, including subactive mode, unless otherwise specified. Item Symbol Applicable Pins Min Typ Max Unit Test Condition Reference Figure Input pin high width t IH IRQ 0 to IRQ4, WKP 0 to WKP 7, ADTRG, TMIF, TMIG, TMCIY 2— — t cyc t subcyc Figure 14.3 Input pin low width t IL IRQ 0 to IRQ4, WKP 0 to WKP 7, ADTRG, TMIF, TMIG, TMCIY 2— — t cyc t subcyc Figure 14.3 |
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