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HD6433635SW Datasheet(PDF) 105 Page - Renesas Technology Corp |
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HD6433635SW Datasheet(HTML) 105 Page - Renesas Technology Corp |
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105 / 418 page  91 Bit 6: STS2 Bit 5: STS1 Bit 4: STS0 Description 0 0 0 Wait time = 8,192 states (initial value) 1 Wait time = 16,384 states 1 0 Wait time = 32,768 states 1 Wait time = 65,536 states 1 ** Wait time = 131,072 states Note: * Don’t care Bit 3—Low Speed on Flag (LSON): This bit chooses the system clock (ø) or subclock (ø SUB) as the CPU operating clock when watch mode is cleared. The resulting operation mode depends on the combination of other control bits and interrupt input. Bit 3: LSON Description 0 The CPU operates on the system clock (ø) (initial value) 1 The CPU operates on the subclock (ø SUB) Bits 2 to 0—Reserved Bits: These bits are reserved; they are always read as 1, and cannot be modified. System Control Register 2 (SYSCR2) Bit 76543210 — — — NESEL DTON MSON SA1 SA0 Initial value 11100000 Read/Write — — — R/W R/W R/W R/W R/W SYSCR2 is an 8-bit read/write register for power-down mode control. Upon reset, SYSCR2 is initialized to H'E0. Bits 7 to 5—Reserved Bits: These bits are reserved; they are always read as 1, and cannot be modified. |
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