HD6433635SW datasheet(107/418 Pages) RENESAS

107 / 418 page

Bits 1 and 0—Subactive Mode Clock Select (SA1 and SA0): These bits select the CPU clock

rate (ø

W/2, øW/4, or øW/8) in subactive mode. SA1 and SA0 cannot be modified in subactive mode.

Bit 1: SA1

Bit 0: SA0

Description

00ø

W/8

(initial value)

1ø

W/4

W/2

Note: * Don’t care

5.2

Sleep Mode

5.2.1

Transition to Sleep Mode

The system goes from active mode to sleep mode when a SLEEP instruction is executed while the

SSBY and LSON bits in system control register 1 (SYSCR1) are cleared to 0. In sleep mode CPU

operation is halted but the on-chip peripheral functions are operational. The CPU register contents

are retained.

5.2.2

Clearing Sleep Mode

Sleep mode is cleared by an interrupt (timer A, timer F, timer G, timer Y, IRQ

0 to IRQ4, WKP0 to

WKP

7, SCI1, SCI3, A/D converter) or by reset input.

Clearing by Interrupt: When an interrupt is requested, sleep mode is cleared and interrupt

exception handling starts. Operation resumes in active (high-speed) mode if MSON = 0 in

SYSCR2, or active (medium-speed) mode if MSON = 1. Sleep mode is not cleared if the I bit of

the condition code register (CCR) is set to 1 or the particular interrupt is disabled in the interrupt

enable register.

Clearing by Reset Input: When the

RES pin goes low, or when a watchdog timer reset is

effected, the CPU goes into the reset state and sleep mode is cleared.

HD6433635SW Datasheet(PDF) 107 Page - Renesas Technology Corp