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HD6433635SW Datasheet(PDF) 277 Page - Renesas Technology Corp |
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HD6433635SW Datasheet(HTML) 277 Page - Renesas Technology Corp |
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277 / 418 page  263 Transmitting processor Receiving processor A Communication line Receiving processor B Receiving processor C Receiving processor D Serial data ID-sending cycle (receiving processor address) Data-sending cycle (data sent to receiving processor designated by ID) (ID = 01) (ID = 02) (ID = 03) (ID = 04) H'01 H'AA (MPB = 1) (MPB = 0) MPB: Multiprocessor bit Figure 10.19 Example of Interprocessor Communication Using Multiprocessor Format (Data H'AA Sent to Receiving Processor A) Four communication formats are available. Parity-bit settings are ignored when a multiprocessor format is selected. For details see table 10.14. For a description of the clock used in multiprocessor communication, see 10.3.4, Operation in Asynchronous Mode. |
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