HD6433635SW datasheet(274/418 Pages) RENESAS

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SCI3 operates as follows when receiving serial data in synchronous mode.

In synchronization with the input or output of the serial clock, SCI3 initializes internally and starts

receiving. Received data is set in RSR from LSB to MSB.

After data has been received, SCI3 checks to confirm that the value of bit RDRF is 0 indicating

that received data can be transferred from RSR to RDR. If this check passes, RDRF is set to 1 and

the received data is stored in RDR. At this time, if bit RIE in SCR3 is set to 1, an RXI interrupt is

requested. If an overrun error is detected, OER is set to 1 and RDRF remains set to 1. Then if bit

RIE in SCR3 is set to 1, an ERI interrupt is requested.

For the overrun error detection conditions and receive data processing, see table 10.15.

Note:

Data receiving cannot be continued while a receive error flag is set. Before continuing the

receive operation it is necessary to clear the OER, FER, PER, and RDRF flags to 0.

Figure 10.17 shows a typical receive operation in synchronous mode.

Serial

clock

Serial

data

RDRF

OER

SCI3

operation

User

processing

Bit 7

Bit 0

Bit 7

Bit 0

Bit 1

Bit 6

Bit 7

1 frame

RXI request RDRF cleared

to 0

RXI request

Read data

from RDR

ERI request due

to overrun error

RDR data

not read

(RDRF = 1)

Overrun error

handling

Figure 10.17 Typical Receive Operation in Synchronous Mode

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