SH7052 datasheet(859/919 Pages) RENESAS

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833

24.3.6

I/O Port Timing

Table 24.11 shows I/O port timing.

Table 24.11 I/O Port Timing

Conditions: V

CC = PLLVCC = 3.3 V ±0.3 V, PVCC1 = 5.0 V ±0.5 V, PVCC2 = 5.0 V ± 0.5 V,

CC = 5.0 V ±0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V,

a = –40°C to 85°C.

When writing or erasing flash EEPROM, T

a = –40°C to 85°C.

Item

Symbol

Min

Max

Unit

Figures

Port output data delay time

PWD

—

100

Figure 24.13

Port input hold time

PRH

24*

24+tcyc

—

Port input setup time

PRS

24*

24+tcyc

—

[Operating precautions]

The operation guaranteed voltage range of power supply PV

CC1 in MCU single-chip mode is 5.0 V

±0.5 V. Do not use a voltage outside this range.

*1 The port input signals are asynchronous, but judged to have been changed at CK clock rise

with two-state intervals shown in figure 24.13. If the setup times shown here are not provided,

recognition is delayed until the clock rise two states after that timing.

tPRS

tPRH

tPWD

Port

(read)

Port

(write)

Figure 24.13 I/O Port Input/Output timing

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