M37540E2GP datasheet(9/366 Pages) RENESAS

9 / 366 page

List of figures

7540 Group

List of figures

CHAPTER 1 HARDWARE

Fig. 1 Pin configuration (32P6U-A type) ..................................................................................... 1-3

Fig. 2 Pin configuration (36P2R-A type) ..................................................................................... 1-3

Fig. 3 Pin configuration (32P4B-A type) ..................................................................................... 1-4

Fig. 4 Pin configuration (42S1M type) ........................................................................................ 1-4

Fig. 5 Functional block diagram (32P6U package) ................................................................... 1-5

Fig. 6 Functional block diagram (36P2R package) ................................................................... 1-6

Fig. 7 Functional block diagram (32P4B package) ................................................................... 1-7

Fig. 8 Memory expansion plan ..................................................................................................... 1-9

Fig. 9 740 Family CPU register structure ................................................................................. 1-11

Fig. 10 Register push and pop at interrupt generation and subroutine call ....................... 1-12

Fig. 11 Structure of CPU mode register ................................................................................... 1-14

Fig. 12 Switching method of CPU mode register .................................................................... 1-14

Fig. 13 Memory map diagram .................................................................................................... 1-15

Fig. 14 Memory map of special function register (SFR) ........................................................ 1-16

Fig. 15 Structure of pull-up control register ............................................................................. 1-17

Fig. 16 Structure of port P1P3 control register ....................................................................... 1-17

Fig. 17 Block diagram of ports (1) ............................................................................................ 1-19

Fig. 18 Block diagram of ports (2) ............................................................................................ 1-20

Fig. 19 Interrupt control ............................................................................................................... 1-22

Fig. 20 Structure of Interrupt-related registers ........................................................................ 1-22

Fig. 21 Connection example when using key input interrupt and port P0 block diagram 1-23

Fig. 22 Structure of timer A mode register .............................................................................. 1-25

Fig. 23 Structure of timer X mode register .............................................................................. 1-26

Fig. 24 Timer count source set register ................................................................................... 1-26

Fig. 25 Structure of timer Y, Z mode register ......................................................................... 1-32

Fig. 26 Structure of timer Y, Z waveform output control register ......................................... 1-32

Fig. 27 Structure of one-shot start register .............................................................................. 1-32

Fig. 28 Block diagram of timer 1 and timer A ......................................................................... 1-33

Fig. 29 Block diagram of timer X, timer Y and timer Z ......................................................... 1-34

Fig. 30 Block diagram of clock synchronous serial I/O1 ........................................................ 1-35

Fig. 31 Operation of clock synchronous serial I/O1 function ................................................ 1-35

Fig. 32 Block diagram of UART serial I/O1 ............................................................................. 1-36

Fig. 33 Operation of UART serial I/O1 function ...................................................................... 1-36

Fig. 34 Structure of serial I/O1-related registers ..................................................................... 1-38

Fig. 35 Structure of serial I/O2 control registers ..................................................................... 1-39

Fig. 36 Block diagram of serial I/O2 ......................................................................................... 1-39

Fig. 37 Serial I/O2 timing (LSB first) ........................................................................................ 1-40

Fig. 38 Structure of A/D control register .................................................................................. 1-41

Fig. 39 Structure of A/D conversion register ........................................................................... 1-41

Fig. 40 Block diagram of A/D converter ................................................................................... 1-41

Fig. 41 Block diagram of watchdog timer ................................................................................. 1-42

Fig. 42 Structure of watchdog timer control register .............................................................. 1-42

Fig. 43 Example of reset circuit ................................................................................................. 1-43

Fig. 44 Timing diagram at reset ................................................................................................ 1-43

Fig. 45 Internal status of microcomputer at reset ................................................................... 1-44

Fig. 46 External circuit of ceramic resonator ........................................................................... 1-45

Fig. 47 External circuit of RC oscillation .................................................................................. 1-45

Fig. 48 External clock input circuit ............................................................................................ 1-45

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