7630 datasheet(64/238 Pages) RENESAS

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7630 Group User’s Manual

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Table 13: Timing requirements

Symbol

Parameter

Limits

Unit

min.

typ.

max.

tW(RESET)

Reset input “L” pulse width

µs

tC(XIN)

External clock input cycle time

100

tWH(XIN)

External clock input “H” pulse width

tWL(XIN)

External clock input “L” pulse width

tC(CNTR)

CNTR0, CNTR1 input cycle time

(except bi-phase counter mode)

1600

CNTR0 input cycle time (bi-phase counter mode)

2000

tWH(CNTR)

CNTR0, CNTR1 input “H” pulse width

(except bi-phase counter mode)

800

CNTR0 input “H” pulse width (bi-phase counter mode)

1000

tWL(CNTR)

CNTR0, CNTR1 input “L” pulse width

(except bi-phase counter mode)

800

CNTR0 input “L” pulse width (bi-phase counter mode)

1000

tL(CNTR0-TX0)

Lag of CNTR0 and TX0 input edges

(bi-phase counter mode)

500

tC(TX0)TX0 input cycle time (bi-phase counter mode)

3200

tWH(TX0)TX0 input “H” pulse width (bi-phase counter mode)

1600

tWL(TX0)TX0 input “L” pulse width (bi-phase counter mode)

1600

tWH(INT)

INT0, INT1 input “H” pulse width

460

tWL(INT)

INT0, INT1 input “L” pulse width

460

tC(SCLK)

Serial I/O clock input cycle time

8· tC(XIN)

tWH(SCLK)

Serial I/O clock input “H” pulse width

4· tC(XIN)

tWL(SCLK)

Serial I/O clock input “L” pulse width

4· tC(XIN)

tSU(SIN–SCLK)

Serial I/O input setup time

200

tH(SCLK–SIN)

Serial I/O input hold time

150

(VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted)

TIMING REQUIREMENTS

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