H83069RF datasheet(32/1003 Pages) RENESAS

32 / 1003 page

Rev. 5.0, 09/04, page 10 of 978

Pin No.

Type

Symbol

FP-100B

TFP-100B

I/O

Name and Function

Data bus

15 to D0

34 to 23,

21 to 18

Input/

output

Data bus: Bidirectional data bus

Bus control

7 to

2 to 5,

88 to 91

Output

Chip select: Select signals for areas 7 to 0

Output

Address strobe: Goes low to indicate valid address

output on the address bus

Output

Read: Goes low to indicate reading from the external

address space

HWR

Output

High write: Goes low to indicate writing to the

external address space; indicates valid data on the

upper data bus (D

15 to D8).

LWR

Output

Low write: Goes low to indicate writing to the

external address space; indicates valid data on the

lower data bus (D

7 to D0).

WAIT

Input

Wait: Requests insertion of wait states in bus cycles

during access to the external address space

DRAM

RFSH

Output

Refresh: Indicates a refresh cycle

interface

2 to

89, 88,

5, 4

Output

Row address strobe

RAS

RAS: Row address strobe

signal for DRAM

Output

Write enable

WE: Write enable signal for DRAM

HWR

UCAS

Output

Upper column address strobe

UCAS

UCAS: Column

address strobe signal for DRAM

LWR

LCAS

Output

Lower column address strobe

LCAS

LCAS: Column

address strobe signal for DRAM

DMA

controller

DREQ

5, 3

Input

DMA request 1 and 0: DMAC activation

requests

(DMAC)

TEND

94, 93

Output

Transfer end 1 and 0: These signals indicate that

the DMAC has ended a data transfer

H83069RF Datasheet(PDF) 32 Page - Renesas Technology Corp

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