M38K02MCFP datasheet(73/328 Pages) RENESAS

73 / 328 page

FUNCTIONAL DESCRIPTION

Rev.2.00

Oct 05, 2006

page 56 of 112

38K0 Group

REJ09B0337-0200

HARDWARE

(3) Internal Memory Interface Part

The internal memory interface part consists of the CPU register

and the memory channel controller.

qCPU register

The CPU register consists of the follows:

•Memory channel operation mode register

•Memory address counter

•End address register

The CPU can set the beginning address into the memory address

counter when the memory channel operation enable bit

(MC_ENB) of EXB interrupt source enable register is “0”. When

this bit is “1”, the write operation from the CPU is invalid and each

access from the external bus causes count-up operation.

qMemory channel controller

The CPU register consists of the follows:

•Main sequencer

•Internal memory request signal generating circuit

•External memory channel request signal generating circuit

•Address end detection circuit

•Terminal end input processing circuit

(4) Transmit/Receive Data Buffer Part

The transmit/receive data buffer part consists of the 8-bit transmit

buffer register (TXBUF) and the 8-bit receive buffer register

(RXBUF).

Both CPU channel and memory channel use the same transmit

buffer register/receive buffer register to transfer a data to an exter-

nal MCU bus.

(5) External Pin

The external bus interface has the following pins to connect with

an external MCU bus.

•Chip select ........................... P34/ExCS

•Address ................................ P37/ExA0

•Data ...................................... P10/DQ0/AN0 to P17/DQ7/AN7

•Read .................................... P36/ExRD

•Write ..................................... P35/ExWR

•Interrupt request .................. P33/ExINT

It also has the following pins to connect with an external DMAC.

Each pin can be programmed for an ordinary port function or a

DMA interface pin function.

•DMA request ........................ P40/ExDREQ/RxD

•DMA acknowledgment ......... P41/ExDACK/TxD

•Terminal count ..................... P42/ExTC/SCLK

It also has the status read select pin (P43/ExA1/SRDY pin) to con-

firm a ready status of the data buffer from an external MCU bus

This pin functions as a port just after reset. The status read select

function can be set by a program.

•Status read select ................ P43/ExA1/SRDY

qCPU channel: Communication with 38K0 group CPU

When a read/write operation is performed from an external MCU

bus in address signal ExA0 = “H”, the interrupt is generated and

the 38K0 group CPU can confirm its access. The 38K0 group CPU

judges the interrupt source and it starts a data transmission/recep-

tion with an external MCU bus.

qMemory channel: Communication with 38K0 group memory

multichannel RAM

When a read/write operation is performed from an external MCU

bus in address signal ExA0 = “L”, access to the multichannel RAM

is performed. Then an address of the multichannel RAM is made

by the external bus interface and it is increased at each access

completion. Consequently, FIFO access is performed.

Even if a read/write operation is performed in DACK = “L” instead

of ExCS = “L” and ExA0 = “L”, FIFO access to the multichannel

RAM is performed.

The beginning address and the end address must be set by the

CPU in advance.

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