TS3V556

5/8

APPLICATION INFORMATION

MONOSTABLE OPERATION

In the monostable mode,the timer functions as a

one-shot. Referring to figure 2 the external capaci-

tor is initially held discharged by a transistor inside

the timer.

V

CC

Reset

Trigger

Out

R

C

Control Voltage

0.01 F

µ

1/2

TS3V556

Figure 2

CAPACITOR VOLTAGE = 2.0V/div

Ω

Ω

µ

t = 0.1 ms / div

INPUT = 2.0V/div

OUTPUT VOLTAGE = 5.0V/div

R = 9.1k , C = 0.01 F , R = 1.0k

L

Figure 3

TYPICAL CHARACTERISTICS

CC

SUPPLY VOLTAGE, V

(V)

300

200

100

04

8

12

16

Figure 1 :

Supply Current (each timer)

versus supply voltage.

The circuit triggers on a negative-going input signal

circuit remains in this state until the set time has

elapsed,even if it is triggered again during this in-

terval. The duration of the output HIGH state is

given by t = 1.1 R x C.

Notice that since the charge rate and the threshold

level of the comparator are both directly propor-

tional to supply voltage, the timing interval is inde-

pendent of supply. Applying a negative pulse

simultaneously to the Reset terminal (pin 4 or 10)

and the Trigger terminal (pin 2 or 8) during the tim-

ing cycle discharges the external capacitor and

causes the cycle to start over. The timing cycle now

starts on the positive edge of the reset pulse. Dur-

ing the time the reset pulse is applied, the output is

driven to its LOW state.

When a negative trigger pulse is applied to the trig-

ger terminal, the flip-flop is set, releasing the short

circuit across the external capacitor and driving the

output HIGH. The voltage across the capacitor in-

creases exponentiallywith the time constant

τ =R x

C.

When the voltage across the capacitor equals 2/3

discharges the capacitor rapidly and drives the out-

put to its LOW state.

Figure 3 shows the actual waveforms generated in

this mode of operation.

When Reset is not used, it should be tied high to

avoid any possible or false triggering.