ADA4062-2ARZ-R7 datasheet(15/20 Pages) AD

15 / 20 page

ADA4062-2

Rev. 0 | Page 15 of

Most JFET input amplifiers have phase reversal if either input

exceeds the input common-mode range.

For the ADA4062-2, the output does not phase reverse if one or

both of the inputs exceeds the input voltage range but stays below

the positive supply rail and 0.5 V above the negative supply rail.

With a supply voltage of ±15 V, phase reversal occurs when the

input voltage is a negative signal greater than −14.5 V. This is due

to saturation of the input stage leading to forward biasing of the

gate-drain diode. Phase reversal in ADA4062-2 can be prevented

by using a Schottky diode to clamp the input terminals to each

other. In the simple buffer circuit in Figure 57, D1 protects the

op amp against phase reversal and R limits the input current

that flows into the op amp.

+VSY

–VSY

10kΩ

ADA4062-2

1/2

IN5711

Figure 57. Phase Reversal Solution Circuit

TIME (40µs/DIV)

VSY = ±15V

VOUT

VIN

Figure 58. No Phase Reversal

ADA4062-2ARZ-R7 Datasheet(PDF) 15 Page - Analog Devices