OPA653IDBVR datasheet(12/19 Pages) TI

12 / 19 page

Input and ESD Protection

External

Internal

Circuitry

-VCC

OPA653

SBOS348 – DECEMBER 2008........................................................................................................................................................................................... www.ti.com

Other network components, such as noninverting

case, and set the series resistor value as shown in

input termination resistors, should also be placed

the plot of RISO vs Capacitive Load (Figure 17). This

close to the package. Even with a low parasitic

configuration does not preserve signal integrity as

capacitance, excessively high resistor values can

well

doubly-terminated

line.

the

input

create significant time constants that can degrade

impedance of the destination device is low, there will

device

performance.

Good

axial

metal

film

be some signal attenuation as a result of the voltage

surface-mount resistors have approximately 0.2 pF in

divider

formed

the

series

output

into

the

shunt with the resistor. For resistor values greater

terminating impedance.

than 1.5 k

Ω, this parasitic capacitance can add a pole

e) Socketing a high-speed part such as the

and/or zero below 500 MHz that can affect circuit

OPA653 is not recommended. The additional lead

operation. Keep resistor values as low as possible.

length and pin-to-pin capacitance introduced by the

Using values less than 500

Ω automatically holds the

socket can create an extremely troublesome parasitic

resistor noise terms low, and minimizes the effects of

network that can make it almost impossible to

parasitic capacitance.

achieve a smooth, stable frequency response. Best

d) Connections to other wideband devices on the

results are obtained by soldering the OPA653 directly

board may be made with short direct traces or

onto the board.

through

onboard

transmission

lines.

For

short

connections, consider the trace and the input to the

next device as a lumped capacitive load. Relatively

The OPA653 is built using a very high-speed

wide traces (50 mils to 100 mils, or 1,27 cm to 2,54

complementary bipolar process. The internal junction

cm) should be used. Estimate the total capacitive

breakdown voltages are relatively low for these very

load and set RISO from the plot of Recommended

small geometry devices. These breakdowns are

RISO vs Capacitive Load (Figure 17). Low parasitic

reflected in the Absolute Maximum Ratings table. All

capacitive loads (less than 5 pF) may not need an

device pins are protected with internal ESD protection

RISO because the OPA653 is nominally compensated

diodes to the power supplies, as Figure 25 shows.

to operate with a 2-pF parasitic load.

Higher parasitic capacitive loads without an RISO are

allowed as the signal gain increases (increasing the

unloaded phase margin). If a long trace is required,

and

the

6-dB

signal

loss

intrinsic

doubly-terminated transmission line is acceptable,

implement a matched impedance transmission line

using microstrip or stripline techniques (consult an

ECL design handbook for microstrip and stripline

layout techniques). A 50-

Ω environment is normally

Figure 25. Internal ESD Protection

not

necessary

onboard,

and

fact

higher

impedance environment improves distortion as shown

the

distortion

versus

load

plots.

With

These diodes provide moderate protection to input

characteristic board trace impedance defined based

overdrive voltages above the supplies as well. The

on board material and trace dimensions, a matching

protection

diodes

can

typically

support

30-mA

series resistor into the trace from the output of the

continuous

current.

Where

higher

currents

are

OPA653 is used as well as a terminating shunt

possible (for example, in systems with ±12-V supply

resistor at the input of the destination device.

parts driving into the OPA653), current limiting series

Remember also that the terminating impedance is the

resistors should be added into the two inputs. Keep

parallel combination of the shunt resistor and the

these resistor values as low as possible because high

input impedance of the destination device: this total

values

degrade

both

noise

performance

and

effective impedance should be set to match the trace

frequency response.

impedance.

the

6-dB

attenuation

doubly-terminated transmission line is unacceptable,

a long trace can be series-terminated at the source

end only. Treat the trace as a capacitive load in this

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