PCA9518AD datasheet(7/23 Pages) NXP

7 / 23 page

PCA9518A_3

Product data sheet

Rev. 03 — 3 December 2008

7 of 23

NXP Semiconductors

PCA9518A

Expandable 5-channel I2C-bus hub

In order to illustrate what would be seen in a typical application, refer to Figure 6. If the

bus master in Figure 5 were to write to the slave through the PCA9518A, we would see

the waveform shown in Figure 6. This looks like a normal I2C-bus transmission except for

the small foot preceding each clock LOW-to-HIGH transition and proceeding each data

LOW-to-HIGH transition for the master. The foot height is the difference between the LOW

level driven by the master and the higher voltage LOW level driven by the PCA9518A

repeater. Its width corresponds to an effective clock stretching coming from the

PCA9518A that delays the rising edge of the clock. That same magnitude of delay is seen

on the rising edge of the data. The foot on the rising edge of the data is extended through

the 9th clock pulse as the PCA9518A repeats the acknowledge from the slave to the

master. The clock of the slave looks normal except the VOL is the ~0.5 V level generated

by the PCA9518A. The SDA at the slave has a particularly interesting shape during the 9th

clock cycle where the slave pulls the line below the value driven by the PCA9518A during

Only two of the ﬁve channels on the PCA9518A Device 2 are being used. EN3 and EN4 are connected to VSS to disable

channels 3 and 4 and/or SDA3/SCL3 and SDA4/SCL4 are pulled up to VDD. SDA0 and SCL0 can be used as a normal I2C-bus

port, but if unused then it must be pulled up to VDD since there is no enable pin.

The pull-ups shown on Device 2 channels 3 and 4 are not required if their enable pins (ENn) are permanently held LOW.

Fig 5.

Typical application: multiple expandable 5-channel I2C-bus hubs

002aac535

VDD

EXPSDA2

EXPSDA1

SCL1

SDA1

VSS

EXPSCL1

EXPSCL2

SUBSYSTEM 1

SDA

SCL

400 kHz

5 V

SCL2

SDA2

SUBSYSTEM 2

SDA

SCL

400 kHz

3.3 V

SCL3

SDA3

SUBSYSTEM 3

SDA

SCL

100 kHz

5 V

SCL4

SDA4

SUBSYSTEM 4

SDA

SCL

100 kHz

3.3 V

PCA9518A

SCL

SDA

EN2

EN1

EN3

EN4

SCL0

SDA0

DEVICE 1

BUS

MASTER

400 kHz

3.3 V

VSS

EN2

EN1

EN3

EN4

SCL4

SDA4

VDD

EXPSDA2

EXPSDA1

EXPSCL1

EXPSCL2

PCA9518A

SCL0

SDA0

DEVICE 2

SCL1

SDA1

SUBSYSTEM 5

SDA

SCL

100 kHz

5 V

SCL2

SDA2

SUBSYSTEM 6

SDA

SCL

400 kHz

3.3 V

SCL3

SDA3

3.3 V

or 5 V

3.3 V

or 5 V

disabled;

not connected

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