ATF1504ASL datasheet(8/35 Pages) ATMEL

8 / 35 page

ATF1504AS(L)

0950O–PLD–7/05

Programmable Pin-

keeper Option for

Inputs and I/Os

The ATF1504AS offers the option of programming all input and I/O pins so that pin-

keeper circuits can be utilized. When any pin is driven high or low and then subse-

quently left floating, it will stay at that previous high- or low-level. This circuitry prevents

unused input and I/O lines from floating to intermediate voltage levels, which causes

unnecessary power consumption and system noise. The keeper circuits eliminate the

need for external pull-up resistors and eliminate their DC power consumption.

Input Diagram

Speed/Power

Management

The ATF1504AS has several built-in speed and power management features. The

ATF1504AS contains circuitry that automatically puts the device into a low-power

standby mode when no logic transitions are occurring. This not only reduces power con-

sumption during inactive periods, but also provides proportional power savings for most

applications running at system speeds below 5 MHz. This feature may be selected as a

device option.

I/O Diagram

To further reduce power, each ATF1504AS macrocell has a Reduced Power bit feature.

This feature allows individual macrocells to be configured for maximum power savings.

This feature may be selected as a design option.

All ATF1504AS also have an optional power-down mode. In this mode, current drops to

below 10 mA. When the power-down option is selected, either PD1 or PD2 pins (or

both) can be used to power-down the part. The power-down option is selected in the

design source file. When enabled, the device goes into power-down when either PD1 or

PD2 is high. In the power-down mode, all internal logic signals are latched and held, as

are any enabled outputs.

ATF1504ASL Datasheet(PDF) 8 Page - ATMEL Corporation