2

ATC18M

4262A–AERO–07/03

Delays to tri-state are defined as delay to turn off (VGS < VT) of the driving devices.

Output pad drain current corresponds to the output current of the pad when the output

voltage is V

resistors (in and out of the die) are taken into account. In order to have accurate timing

estimates, all characterization has been run on electrical netlists extracted from the lay-

out database.

Standard Cell Library

SClib

The Atmel Standard Cell Library, SClib, contains a comprehensive set of a combination

of logic and storage cells. The SClib library includes cells that belong to the following

categories:

• Buffers and Gates

• Multiplexers

•Flip-flops

•Scan Flip-flops

•Latches

• Adders and Subtractors

Decoding the Cell Name

Table 2 shows the naming conventions for the cells in the SClib library. Each cell name

begins with either a two-, three-, or four-letter code that defines the type of cell. This

indicates the range of standard cells available.

Table 2. Cell Codes

Code

Description

Code

Description

AD

Adder

INVB

Balanced Inverter

AH

Half Adder

INVT

Inverting Tri-state Buffer

AS

Adder/Subtractor

LA

D Latch

AN

AND Gate

MI

Inverting Multiplexer

AOI

AND-OR-Invert Gate

MX

Multiplexer

AON

AND-OR-AND-Invert Gates

ND

NAND Gate

AOR

AND-OR Gate

NR

NOR Gate

BUFB

Balanced Buffer

OAI

OR-AND-Invert Gate

BUFF

Non-Inverting Buffer

OAN

OR-AND-OR-Invert Gates

BUFT

Non-Inverting Tri-state Buffer

OR

OR Gate

CG

Carry Generator

ORA

OR-AND Gate

CLK2

Clock Buffer

SD

Multiplexed Scan D Flip-flop

DF

D Flip-flop

SRLA

Set/Reset Latches with NAND input

DLA

Dual Input Latches

SU

Subtractor

H...

SEU Hardened Versions

XN

Exclusive NOR Gate

INV0

Inverter

XR

Exclusive OR Gate