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SMF3.3

PROTECTION PRODUCTS

SMF3.3

Applications Information

Circuit Board Layout Recommendations for Suppres-

sion of ESD.

Good circuit board layout is critical for the suppression

of ESD induced transients. The following guidelines are

recommended:

Place the TVS near the input terminals or connec-

tors to restrict transient coupling.

Minimize the path length between the TVS and the

protected line.

Minimize all conductive loops including power and

ground loops.

The ESD transient return path to ground should be

kept as short as possible.

Never run critical signals near board edges.

Use ground planes whenever possible.

Matte Tin Lead Finish

Matte tin has become the industry standard lead-free

replacement for SnPb lead finishes. A matte tin finish

is composed of 100% tin solder with large grains.

Since the solder volume on the leads is small com-

pared to the solder paste volume that is placed on the

land pattern of the PCB, the reflow profile will be

determined by the requirements of the solder paste.

Therefore, these devices are compatible with both

lead-free and SnPb assembly techniques. In addition,

unlike other lead-free compositions, matte tin does not

have any added alloys that can cause degradation of

the solder joint.

Typical Application Diagram