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6201C–PMAAC–31-Jul-07

AT73C239

8.

Normal Procedure

The State Machine monitors the XRESIN pin and provides the proper XRESO pin signal when

reset occurs.

Through the Two-wire Interface (TWI), the user can control and change the output voltage deliv-

ered by LDO1, LDO2, LDO3 and LDO4.

9.

Two-wire Interface (TWI) Protocol

The two-wire interface interconnects components on a unique two-wire bus, made up of one

clock line and one data line with speeds up to 400 Kbits per second, based on a byte oriented

transfer format. The TWI is slave only and has single byte access.

The TWI adds flexibility to the power supply solution, enabling LDO regulators to be controlled

depending on the instantaneous application requirements.

The AT73C239 has the following 7-bit address: 1001000.

Attempting to read data from register addresses not listed in this section results in 0xFF being

read out.

• TWCK is an input pin for the clock

• TWD is an open-drain pin driving or receiving the serial data

The data put on TWD line must be 8 bits long. Data is transferred MSB first. Each byte must be

followed by an acknowledgement.

Each transfer begins with a START condition and terminates with a STOP condition.

• A high-to-low transition on TWD while TWCK is high defines a START condition.

• A low-to-high transition on TWD while TWCK is high defines a STOP condition.

Figure 9-1.

START and STOP Conditions

Figure 9-2.

Transfer Format

After the host initiates a START condition, it sends the 7-bit slave address defined above to

notify the slave device. A read/write bit follows (read = 1, write = 0).

TWD

TWCK

Start

Stop

TWD

TWCK

Start

Address

R/W

Ack

Data

Ack

Data

Ack

Stop