TC534CPL datasheet(12/15 Pages) TELCOM

12 / 15 page

3-58

TELCOM SEMICONDUCTOR, INC.

5V PRECISION DATA ACQUISITION

SUBSYSTEMS

TC530

TC534

Figure 6. TC530/534 Typical Application

RESET

EOC

VCCD

VDD

OUT

CLK

X1: 2MHz

100k

100

Ω

µF

TC04

(1.25V VREF)

(1.03V)

R/W

ACOM

OSC

OUT

DGND

0.22

µF

0.33

µF

INT

100k

TC534

INT

Analog

Inputs

Channel

Control

.01

µF

MUX

IN1

–

IN2

–

IN3

–

IN4

–

+5V

–5V

(Optional)

BUF

REF

–

REF

–

REF

0.22

µF

CAP

CAP –

µF

+5V

INT

PROCESSOR

I/O

.01

µF

.01

µF

3. Calculate LOAD VALUE

LOAD VALUE = 256 – (tINT)(FIN)/1024 = [128]10

[128]10 = 80 hex

4. Calculate RINT

RINT (in MΩ) = VINMAX/20 = 2/20 = 100kΩ

5. Calculate CINT for maximum (4V) integrator out-

put swing

CINT (in µF) = (tINT)(20 x 10 –6)/ (VS – 0.9)

= (.066)(20 x 10 –6)/(4.1)

= .32

µF (use closest value: 0.33µF)

NOTE: TelCom recommended capacitor:

WIMA p/n: MK12 .33/63/10

6. Choose CREF and CAZ based on conversion rate

Conversions/sec = 1/(tAZ + tINT + 2tINT + 2msec)

= 1/(66msec + 66msec + 132msec

+ 2msec)

= 3.7 conversions/sec

from which CAZ = CREF = 0.22µF (see Table 1)

NOTE: TelCom recommended capacitor:

WIMA p/n: MK12 .22/63/10

7. Calculate VREF

VREF (in Volts = (VS – 0.9)(CINT)(RINT)

2(tINT)

= (4.1)(0.33x10 –6)(105)/2(.066)

= 1.025V

Power Supply Sequencing

Improper sequencing of the power supply inputs (VDD

vs. VCCD) can potentially cause an improper power-up

sequence to occur. See

Circuit Design/Layout Consider-

ations below. Failing to insure a proper power-up sequence

can cause spurious operation.

Ciruit Design/Layout Considerations

(1) Separate ground return paths should be used for the

analog and digital circuitry. Use of ground planes and trace

fill on analog circuit sections is highly recommended

EXCEPT for in and around the integrator section and

CREF, CAZ. (CINT, CREF, CAZ, RINT). Stray capacitance be-

tween these nodes and ground appears in parallel with the

components themselves and can affect measurement accu-

racy.

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