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TC7117ACPL Datasheet(PDF) 10 Page - TelCom Semiconductor, Inc

Part # TC7117ACPL
Description  3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS WITH HOLD
PDF  14 Pages
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Manufacturer  TELCOM [TelCom Semiconductor, Inc]
Direct Link  http://www.telcom-semi.com
Logo TELCOM - TelCom Semiconductor, Inc

TC7117ACPL Datasheet(HTML) 10 Page - TelCom Semiconductor, Inc

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3-212
TELCOM SEMICONDUCTOR, INC.
3-1/2 DIGIT ANALOG-TO-DIGITAL
CONVERTERS WITH HOLD
TC7116
TC7116A
TC7117
TC7117A
TC7117
TC7117A
THOUSANDS
HUNDREDS
TENS
UNITS
4
39
OSC
V
DIGITAL
GND
TEST
35
TO SWITCH DRIVERS
FROM COMPARATOR OUTPUT
CLOCK
7-SEGMENT
DECODE
7-SEGMENT
DECODE
7-SEGMENT
DECODE
40
38
2
OSC3
OSC1
÷
HLDR
CONTROL LOGIC
TYPICAL SEGMENT OUTPUT
DIGITAL GROUND
TO
SEGMENT
V
+
0.5 mA
8 mA
37
21
500
Ω
V
+
1
LATCH
~70 k
Ω
+
System Timing
The clocking method used for the TC7116/TC7116A
and TC7117/TC7117A is shown in Figure 9. Three clocking
methods may be used:
(1) An external oscillator connected to pin 40.
(2) A crystal between pins 39 and 40.
(3) An RC network using all three pins.
The oscillator frequency is
4 before it clocks the
decade counters. It is then further divided to form the three
convert-cycle phases: signal integrate (1000 counts), refer-
ence deintegrate (0 to 2000 counts), and auto-zero (1000 to
3000 counts). For signals less than full scale, auto-zero gets
the unused portion of reference deintegrate. This makes a
complete measure cycle of 4000 (16,000 clock pulses)
independent of input voltage. For 3 readings per second, an
oscillator frequency of 48 kHz would be used.
To achieve maximum rejection of 60-Hz pickup, the
signal-integrate cycle should be a multiple of 60 Hz. Oscil-
lator frequencies of 240 kHz, 120 kHz, 80 kHz, 60 kHz, 48
kHz, 40 kHz, etc. should be selected. For 50 Hz rejection,
oscillator frequencies of 200 kHz, 100 kHz, 66-2/3 kHz, 50
kHz, 40 kHz, etc. would be suitable. Note that 40 kHz (2.5
readings per second) will reject both 50 Hz and 60 Hz.
HOLD Reading Input
When HLDR is at a logic HIGH the latch will not be
updated. Analog-to-digital conversions will continue but will
not be updated until HLDR is returned to LOW. To continu-
ously update the display, connect to test (TC7116/TC7116A)
or ground (TC7117/TC7117A), or disconnect. This input is
CMOS compatible with 70 k
Ω typical resistance to TEST
(TC7116/TC7116A) or ground (TC7117/TC7117A).
Figure 9. TC7117/TC7117A Digital Section



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