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AX2000-1CGG896 Datasheet(PDF) 85 Page - Actel Corporation |
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AX2000-1CGG896 Datasheet(HTML) 85 Page - Actel Corporation |
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85 / 226 page  Axcelerator Family FPGAs v2.7 2-71 Clock Skew Minimization Figure 2-56 indicates how feedback from the clock network can be used to create minimal skew between the distributed clock network and the input clock. The input clock is fed to the reference clock input of the PLL. The output clock (CLK2) feeds a routed clock network. The feedback input to the PLL uses a clock input delayed by a routing network. The PLL then adjusts the phase of the input clock to match the delayed clock, thus providing nearly zero effective skew between the two clocks. Refer to Actel’s Axcelerator Family PLL and Clock Management application note for more information. Figure 2-56 • Using the PLL for Clock Deskewing QCLR Delay Line PLL RefCLK FB 6 /j 6 CLK1 PowerDown Input Clock Clock Network Lock CLK2 FBMuxSel 5 DividerI DelayLine DividerJ LowFreq 3 Osc ÷1 133 MHz 133 MHz D Q SET 133 MHz Delay Line /i /i Delay Match /i Delay Match |
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