5

LTC4301

4301fb

OPERATIO

Start-Up

either during power-up or live insertion, it starts in an

undervoltage lockout (UVLO) state, ignoring any activity

This is to ensure that the part does not try to function until

it has enough voltage to do so.

During this time, the 1V precharge circuitry is active and

forces 1V through 200k nominal resistors to the SDA and

SCL pins. Because the I/O card is being plugged into a live

backplane, the voltage on the backplane SDA and SCL

the SCL and SDA pins to 1V minimizes the worst-case

voltage differential these pins will see at the moment of

connection, therefore minimizing the amount of distur-

bance caused by the I/O card.

Once the LTC4301 comes out of UVLO, it assumes that

SDAIN and SCLIN have been inserted into a live system

and that SDAOUT and SCLOUT are being powered up at

the same time as itself. Therefore, it looks for either a stop

bit or bus idle condition on the backplane side to indicate

the completion of a data transaction. When either one

occurs, the part also verifies that both the SDAOUT and

SCLOUT voltages are high. When all of these conditions

are met, the input-to-output connection circuitry is acti-

vated, joining the SDA and SCL busses on the I/O card with

those on the backplane.

Connection Circuitry

Once the connection circuitry is activated, the functional-

ity of the SDAIN and SDAOUT pins is identical. A low

forced on either pin at any time results in both pin voltages

being low. For proper operation, logic low input voltages

should be no higher than 0.4V with respect to the ground

pin voltage of the LTC4301. SDAIN and SDAOUT enter a

logic high state only when all devices on both SDAIN and

SDAOUT release high. The same is true for SCLIN and

SCLOUT. This important feature ensures that clock stretch-

ing, clock synchronization, arbitration and the acknowl-

edge protocol always work, regardless of how the devices

in the system are tied to the LTC4301.

Another key feature of the connection circuitry is that it

provides bidirectional buffering, keeping the backplane

and card capacitances isolated. Because of this isolation,

the waveforms on the backplane busses look slightly

different than the corresponding card bus waveforms as

described here.

Input-to-Output Offset Voltage

LTC4301’s data or clock pins, the LTC4301 regulates the

slightly higher voltage, as directed by the following

equation:

where R is the bus pull-up resistance in ohms. For ex-

= 3.3V and the pull-up resistor R on SDAIN is 10k, then the

voltage on SDAIN = 10mV + 75mV + (3.3/10000) • 70 =

108mV (typical). See the Typical Performance Character-

istics section for curves showing the offset voltage as a

Propagation Delays

During a rising edge, the rise time on each side is deter-

mined by the bus pull-up resistor and the equivalent

capacitance on the line. If the pull-up resistors are the

same, a difference in rise time occurs which is directly

proportional to the difference in capacitance between

the two sides. This effect is displayed in Figure 1 for

one side and 20pF on the other). SDAIN and SCLIN are

pulled-up to 3.3V, and SDAOUT and SCLOUT are pulled-

up to 5V. Since the output side has less capacitance than

the input, it rises faster and the effective low to high

propagation delay is negative.

Figure 1. Input-Output Connection

4301 F01

OUTPUT

SIDE

20pF

INPUT

SIDE

55pF

1

µs/DIV

1V/DIV