LTC2923IDE datasheet(17/20 Pages) LINER

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LTC2923

2923fa

Layout Considerations

Be sure to place a 0.1µF bypass capacitor as near as

possible to the supply pin of the LTC2923. A 10Ω resistor

located near the FET and connected between the FET’s

gate and the external CGATE capacitor is recommended.

This will almost assuredly eliminate the troublesome high

frequency oscillations that can occur due to the FET

interacting with PCB parasitics.

To minimize the noise on the slave supplies’ outputs, keep

the traces connecting the FBx pins of the LTC2923 and the

feedback nodes of the slave supplies as short as possible.

In addition, do not route those traces next to signals with

fast transition times. In some circumstances it might be

advantageous to add a resistor near the feedback node of

the slave supply in series with the FBx pin of the LTC2923.

This resistor must not exceed:

SERIES

MAX

⎛

⎝

⎜

⎞

⎠

⎟

()

.–

–||

This resistor is most effective if there is already a capacitor

at the feedback node of the slave supply (often a compen-

sation component). Increasing the capacitance on a slave

supply’s feedback node will further improve the noise

immunity, but could affect the stability and transient

response of the supply.

APPLICATIO S I FOR ATIO

VCC

OUT

FET

RFA

RFB

RSERIES

CGATE

10Ω

MINIMIZE

TRACE

LENGTH

VCC

LTC2923

2923 F21

RAMP

FB1

GATE

GND

0.1µF

DC/DC

OUT

Figure 21. Layout Considerations

MASTER

1ms/DIV

2923 F18

Figure 18. Weak Resistive Load

1V/DIV

SLAVE2

SLAVE1

1V/DIV

1ms/DIV

2923 F20

SLAVE2

SLAVE1

MASTER

Figure 20. ON Pin Delayed

Figure 19. Power Supply Start-Ups Delayed

1V/DIV

1ms/DIV

2923 F19

SLAVE2

SLAVE1

MASTER

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