74ACT11652

OCTAL BUS TRANSCEIVER AND REGISTER

WITH 3-STATE OUTPUTS

SCAS087A – APRIL 1993 – REVISED APRIL 1996

3

POST OFFICE BOX 655303

FUNCTION TABLE

INPUTS

DATA I/O†

OPERATION OR FUNCTION

GAB

GBA

CAB

CBA

SAB

SBA

A1–A8

B1–B8

OPERATION OR FUNCTION

L

H

H or L

H or L

X

X

Input

Input

Isolation

L

H

↑

↑

X

X

Input

Input

Store A and B data

X

H

↑

H or L

X

X

Input

Unspecified†

Store A, hold B

H

H

↑

↑

X‡

X

Input

Output

Store A in both registers

L

X

H or L

↑

X

X

Unspecified†

Input

Hold A, store B

L

L

↑

↑

X

X‡

Output

Input

Store B in both registers

L

L

X

X

X

L

Output

Input

Real-time B data to A bus

L

LX

H or L

X

H

Output

Input

Stored B data to A bus

H

H

X

X

L

X

Input

Output

Real-time A data to B bus

H

H

H or L

XH

X

Input

Output

Stored A data to B bus

H

L

H or L

H or L

H

H

Output

Output

Stored A data to B bus and

stored B data to A bus

† The data-output functions may be enabled or disabled by various signals at the GAB or GBA inputs. Data-input functions are always enabled,

i.e., data at the bus terminals is stored on every low-to-high transition on the clock inputs.

‡ Select control = L: clocks can occur simultaneously. Select control = H: clocks must be staggered to load both registers.

§ This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

5

5

B8

B7

B6

B5

B4

B3

B2

B1

17

18

19

20

23

24

25

26

A8

A7

A6

A5

A4

A3

A2

A1

SAB

CAB

SBA

CBA

GBA

2

27

28

15

16

14

1

6D

7

7

4D

G7

C6

G5

C4

EN2 [AB]

EN1 [BA]

2

1

≥1

≥1

1

1

GBA

3

4

5

10

11

12

13