CD74HC652 datasheet(11/12 Pages) TI

11 / 12 page

FIGURE 6. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,

AND PROPAGATION DELAY TIMES FOR EDGE

TRIGGERED SEQUENTIAL LOGIC CIRCUITS

FIGURE 7. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,

AND PROPAGATION DELAY TIMES FOR EDGE

TRIGGERED SEQUENTIAL LOGIC CIRCUITS

FIGURE 8. HC THREE-STATE PROPAGATION DELAY

WAVEFORM

FIGURE 9. HCT THREE-STATE PROPAGATION DELAY

WAVEFORM

NOTE:

Open drain waveforms tPLZ and tPZL are the same as those for three-state shown on the left. The test circuit is Output RL =1kΩ to

VCC, CL = 50pF.

FIGURE 10. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT

Test Circuits and Waveforms (Continued)

trCL

tfCL

GND

VCC

GND

VCC

50%

90%

10%

GND

CLOCK

INPUT

DATA

INPUT

OUTPUT

SET, RESET

OR PRESET

VCC

50%

90%

10%

50%

90%

tREM

tPLH

tSU(H)

tTLH

tTHL

tH(L)

tPHL

50pF

tSU(L)

tH(H)

trCL

tfCL

GND

1.3V

2.7V

0.3V

GND

CLOCK

INPUT

DATA

INPUT

OUTPUT

SET, RESET

OR PRESET

1.3V

90%

10%

1.3V

90%

tREM

tPLH

tSU(H)

tTLH

tTHL

tH(L)

tPHL

50pF

tSU(L)

1.3V

tH(H)

1.3V

50%

10%

90%

GND

VCC

10%

90%

50%

OUTPUT

DISABLE

OUTPUT LOW

TO OFF

OUTPUT HIGH

TO OFF

OUTPUTS

ENABLED

OUTPUTS

DISABLED

OUTPUTS

ENABLED

6ns

tPZH

tPHZ

tPZL

tPLZ

0.3

2.7

GND

10%

90%

1.3V

OUTPUT

DISABLE

OUTPUT LOW

TO OFF

OUTPUT HIGH

TO OFF

OUTPUTS

ENABLED

OUTPUTS

DISABLED

OUTPUTS

ENABLED

6ns

tPZH

tPHZ

tPZL

tPLZ

6ns

1.3

IC WITH

THREE-

STATE

OUTPUT

OTHER

INPUTS

TIED HIGH

OR LOW

OUTPUT

DISABLE

VCC FOR tPLZ AND tPZL

GND FOR tPHZ AND tPZH

OUTPUT

RL = 1kΩ

50pF

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