CDC328A

1-LINE TO 6-LINE CLOCK DRIVER

WITH SELECTABLE POLARITY

SCAS327B – DECEMBER 1992 – REVISED NOVEMBER 1995

1

POST OFFICE BOX 655303

and Clock-Generation Applications

Outputs

Complementary Outputs

Switching Noise

Significantly Reduces Power Dissipation

Small-Outline (D) and Shrink Small-Outline

(DB) Packages

description

The CDC328A contains a clock-driver circuit that distributes one input signal to six outputs with minimum skew

for clock distribution. Through the use of the polarity-control inputs (T/C), various combinations of true and

complementary outputs can be obtained.

The CDC328A is characterized for operation from – 40

°C to 85°C.

FUNCTION TABLE

INPUTS

OUTPUT

T/C

A

Y

L

L

L

L

HH

H

LH

H

H

L

12

A

N1

15

N2

13

1Y1

16

1

1Y2

2

1

2Y1

3

2

N3

10

N4

9

2Y2

5

2

3Y

6

3

4Y

8

4

1T/C

2T/C

3T/C

4T/C

† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Copyright

© 1995, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

EPIC-

ΙΙB is a trademark of Texas Instruments Incorporated.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

D OR DB PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

GND

1Y2

2Y1

GND

2Y2

3Y

GND

4Y

1Y1

1T/C

2T/C

A

3T/C

4T/C