CDC391

1-LINE TO 6-LINE CLOCK DRIVER

WITH SELECTABLE POLARITY AND 3-STATE OUTPUTS

SCAS334A – DECEMBER 1992 – REVISED NOVEMBER 1995

5

POST OFFICE BOX 655303

PARAMETER MEASUREMENT INFORMATION

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT FOR OUTPUTS

S1

7 V

Open

GND

500

Ω

500

Ω

TEST

tPLH/tPHL

tPLZ/tPZL

tPHZ/tPZH

S1

Open

7 V

Open

Output

Control

(low-level

enabling)

Output

Waveform 1

S1 at 7 V

(see Note B)

Output

Waveform 2

S1 at Open

(see Note B)

VOL

VOH

tPZL

tPZH

tPLZ

tPHZ

1.5 V

1.5 V

3.5 V

0 V

1.5 V

VOL + 0.3 V

1.5 V

VOH – 0.3 V

≈ 0 V

3 V

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

tPLH

tPHL

Output

1.5 V

1.5 V

3 V

0 V

1.5 V

VOH

VOL

Input

0.8 V

2 V

tf

0.8 V

2 V

tr

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR

≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.

D. The outputs are measured one at a time with one transition per measurement.

Figure 1. Load Circuit and Voltage Waveforms