CDC857-2, CDC857-3

2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS

SCAS627A – SEPTEMBER 1999 – DECEMBER 1999

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POST OFFICE BOX 655303

Double Data Rate Synchronous DRAM

Applications

Ten Differential Outputs

Used to Synchronize the Outputs to the

Clock Input

Shrink Small-Outline Package (TSSOP)

Capability to Reduce EMI

description

The CDC857-2 and CDC857-3 are high-perfor-

mance, low-skew, low-jitter, phase-lock loop

(PLL) clock driver. They use a PLL to precisely

align, in both frequency and phase, the feedback

(FBOUT) output to the clock (CLK) input signal.

The CDC857-3 operates at 3.3 V (PLL) and 2.5 V

(output buffer). The CDC857-2 operates at

2.5 V (PLL and output buffer).

One bank of ten inverting and noninverting

outputs provide ten low-skew, low-jitter copies of

CLK. Output signal duty cycles are adjusted to

50%, independent of the duty cycle at CLK.

All outputs can be enabled or disabled via a single output enable input. When the G input is high, the outputs

switch in phase and frequency with CLK; when the G input is low, the outputs are disabled to high impedance

state (3-state).

Unlike many products containing PLLs, the CDC857 does not require external RC networks. The loop filter for

the PLL is included on-chip, minimizing component count, board space, and cost.

Because it is based on PLL circuity, the CDC857 requires a stabilization time to achieve phase lock of the

feedback signal to the reference signal. This stabilization time is required following power up and application

of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or

for operation from 0

°C to 85°C.

Copyright

© 1999, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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GND

Y0

Y0

Y1

Y1

GND

GND

Y2

Y2

CLK

CLK

AGND

GND

Y3

Y3

Y4

Y4

GND

GND

Y5

Y5

Y6

Y6

GND

GND

Y7

Y7

G

FBIN

FBIN

FBOUT

FBOUT

GND

Y8

Y8

Y9

Y9

GND

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