CDC925 datasheet(3/18 Pages) TI

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CDC925

133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS

WITH 3-STATE OUTPUTS

SCAS633 – JULY 28, 1999

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

3V66 [0–3]

21, 22, 25, 26

3.3 V, Type 5, 66-MHz clock outputs

48MHz

3.3 V, Type 3, 48-MHz clock output

APIC [0–2]

53, 54, 55

2.5 V, Type 1, APIC clock outputs

CPU [0–3]

41, 42, 45, 46

2.5 V, Type 1, CPU clock outputs

CPU_DIV2 [0–1]

49, 50

2.5 V, Type 1, CPU_DIV2 clock outputs

CPU_STOP

Disables CPU clock to low state

GND

1, 7, 13, 19,

20, 24, 29, 38,

40, 44, 48, 52

Ground

PCI [1–7]

9, 11, 12, 14,

15, 17, 18

3.3 V, Type 5, 33-MHz PCI clock outputs

PCI_F

Free-running 3.3-V, Type 5, 33-MHz PCI clock output

PCI_STOP

Disables PCI clock to low state

PWR_DWN

Power down for complete device with outputs forced low

REF0, REF1

2, 3

3.3 V, Type 3, 14.318-MHz reference clock output

SEL0, SEL1

32, 33

LVTTL level logic select terminals for function selection

SEL133/100

LVTTL level logic select pins for enabling 100/133 MHz

SPREAD

Disables SSC function

VDD3.3V

4, 10, 16, 23,

27, 31, 39

Power for the 3V66, 48MHz, PCI, REF outputs and CORE logic

VDD2.5V

43, 47, 51, 56

Power for CPU and APIC outputs

XIN

Crystal input – 14.318 MHz

XOUT

Crystal output – 14.318 MHz

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