PCI4450 datasheet(39/197 Pages) TI

39 / 197 page

PCI4450 GFN/GJG

PC Card and OHCI Controller

SCPS046 – JANUARY 1999

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

CardBus device class power management

The

PCI Bus Interface Specification for PCI-to-CardBus Bridges was approved by PCMCIA in December of

1997. This specification follows the device and bus state definitions provided in the

PCI Bus Power

Management Interface Specification published by the PCI Special Interest Group (SIG). The main issue

addressed in the

PCI Bus Interface Specification for PCI-to-CardBus Bridges is wake-up from D3hot or D3cold

without losing wake-up context (also called PME context).

The specific issues addressed by the

PCI Bus Interface Specification for PCI-to-CardBus Bridges for D3 wake

up are as follows:

D Preservation of device context: The PCI Power Management Specification version 1.0 states that PRST

must be asserted when transitioning from D3cold to D0. Some method to preserve wake-up context must

be implemented so that PRST does not clear the PME context registers.

D Power source in D3cold if wake-up support is required from this state.

The Texas Instruments PCI4450 addresses these D3 wake-up issues in the following manner:

D Preservation of device context: When PRST is asserted, bits required to preserve PME context are not

cleared. To clear all bits in the PCI4450, another reset pin is defined: G_RST (global reset). G_RST is

normally only asserted during the initial power-on sequence. After the initial boot, PRST should be asserted

so that PME context is retained for D3-to-D0 transitions. Bits cleared by G_RST, but not cleared by PRST

(if the PME enable bit is set), are referred to as PME context bits. Please refer to the master list of PME

context bits in the next section.

D Power source in D3cold if wake-up support is required from this state. Since VCC is removed in D3cold, an

auxiliary power source must be switched to the PCI4450 VCC pins. This switch should be a make before

break type of switch, so that VCC to the PCI4450 is not interrupted.

master list of PME context bits and global reset only bits

PME context bit means that the bit is cleared only by the assertion of G_RST when the PME enable bit is set

(PCI offset A4h, bit 8). If PME is not enabled, then these bits are cleared when either PRST or G_RST is

asserted.

Global reset only bits, as the name implies, are only cleared by G_RST. These bits are never cleared by PRST

regardless of the setting of the PME enable bit. (PCI offset A4h, bit 8). The G_RST signal is gated only by the

SUSPEND signal. This means that assertion of SUSPEND blocks the G_RST signal internally, thus preserving

all register contents.

PCI4450 Datasheet(PDF) 39 Page - Texas Instruments