SN54LS173AFK datasheet(8/19 Pages) TI

8 / 19 page

SN54173, SN54LS173A, SN74173, SN74LS173A

4-BIT D-TYPE REGISTERS

WITH 3-STATE OUTPUTS

SDLS067A – OCTOBER 1976 – REVISED JUNE 1999

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

switching characteristics, VCC = 5 V, TA = 25°C, RL = 667 Ω (see Figure 2)

PARAMETER

TEST CONDITIONS

SN54LS173A

SN74LS173A

UNIT

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

MIN

TYP

MAX

UNIT

fmax

Maximum clock frequency

MHz

tPHL

Propagation delay time,

high-to-low-level output from clear input

tPLH

Propagation delay time,

low-to-high-level output from clock input

CL = 45 pF

tPHL

Propagation delay time,

high-to-low-level output from clock input

tPZH

Output enable time to high level

tPZL

Output enable time to low level

tPHZ

Output disable time from high level

CL =5 pF

tPLZ

Output disable time from low level

CL = 5 pF

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