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SN54GTL16612WD Datasheet(PDF) 4 Page - Texas Instruments

Part # SN54GTL16612WD
Description  18-BIT LVTTL-TO-GTL/GTL UNIVERSAL BUS TRANSCEIVERS
PDF  13 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

SN54GTL16612WD Datasheet(HTML) 4 Page - Texas Instruments

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Absolute Maximum Ratings
(1)
Recommended Operating Conditions
(1) (2) (3) (4)
SN54GTL16612, SN74GTL16612
18-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS
SCBS480K – JUNE 1994 – REVISED JULY 2005
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
3.3 V
–0.5
4.6
VCC
Supply voltage range
V
5 V
–0.5
7
A-port and control inputs
–0.5
7
VI
Input voltage range(2)
V
B port and VREF
–0.5
4.6
A port
–0.5
7
VO
Voltage range applied to any output in the high or power-off state(2)
V
B port
–0.5
4.6
A port
128
IO
Current into any output in the low state
mA
B port
80
IO
Current into any A-port output in the high state(3)
64
mA
Continuous current through each VCC or GND
±100
mA
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
DGG package
64
θ
JA
Package thermal impedance(4)
°C/W
DL package
56
Tstg
Storage temperature range
–65
150
°C
(1)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3)
This current flows only when the output is in the high state and VO > VCC.
(4)
The package thermal impedance is calculated in accordance with JESD 51-7.
SN54GTL16612
SN74GTL16612
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
3.3 V
3.15
3.3
3.45
3.15
3.3
3.45
VCC
Supply voltage
V
5 V
4.75
5
5.25
4.75
5
5.25
GTL
1.14
1.2
1.26
1.14
1.2
1.26
Termination
VTT
V
voltage
GTL+
1.35
1.5
1.65
1.35
1.5
1.65
GTL
0.74
0.8
0.87
0.74
0.8
0.87
VREF
Reference voltage
V
GTL+
0.87
1
1.1
0.87
1
1.1
B port
VTT
VTT
VI
Input voltage
V
Except B port
5.5
5.5
B port
VREF + 50 mV
VREF + 50 mV
High-level
VIH
V
input voltage
Except B port
2
2
B port
VREF – 50 mV
VREF – 50 mV
Low-level
VIL
V
input voltage
Except B port
0.8
0.8
IIK
Input clamp current
–18
–18
mA
High-level
IOH
A port
–32
–32
mA
output current
A port
64
64
Low-level
IOL
mA
output current
B port
40
40
TA
Operating free-air temperature
–55
125
–40
85
°C
(1)
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
(2)
Normal connection sequence is GND first, VCC = 5 V second, and VCC = 3.3 V, I/O, control inputs, VTT and VREF (any order) last.
(3)
VTT and RTT can be adjusted to accommodate backplane impedances if the dc recommended IOL ratings are not exceeded.
(4)
VREF can be adjusted to optimize noise margins, but normally is two-thirds VTT.
4



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