SN74ACT7882

2048

× 18

CLOCKED FIRST-IN, FIRST-OUT MEMORY

SCAS445C – JUNE 1994 – REVISED APRIL 1998

14

POST OFFICE BOX 655303

APPLICATION INFORMATION

expanding the SN74ACT7882

The SN74ACT7882 is expandable in both word width and word depth. Word-depth expansion is accomplished

by connecting the devices in series such that data flows through each device in the chain. Figure 8 shows two

SN74ACT7882 devices configured for depth expansion. The common clock between the devices can be tied

to either the write clock (WRTCLK) of the first device or the read clock (RDCLK) of the last device. The

output-ready (OR) flag of the previous device and the input-ready (IR) flag of the next device maintain data flow

to the last device in the chain whenever space is available.

Figure 9 is an example of two SN74ACT7882 devices in word-width expansion. Width expansion is

accomplished by simply connecting all common control signals between the devices and creating composite

IR and OR signals. The almost-full/almost-empty (AF/AE) flag and half-full (HF) flag can be sampled from any

one device. Depth expansion and width expansion can be used together.

SN74ACT7882

CLOCK

WRTCLK

WRTEN1

WRTEN2

IR

D0–D17

5 V

WRTCLK

WRTEN1

WRTEN2

IR

D0–D17

RDCLK

OR

RDEN1

RDEN2

OE

Q0–Q17

SN74ACT7882

WRTCLK

WRTEN1

WRTEN2

IR

D0–D17

RDCLK

RDEN1

RDEN2

OR

OE

Q0–Q17

RDCLK

RDEN1

RDEN2

OR

Q0–Q17

OE

Figure 8. Word-Depth Expansion: 4096

× 18 Bits

SN74ACT7882

WRTCLK

WRTEN1

WRTEN2

IR

D0–D17

RDCLK

RDEN1

RDEN2

OR

OE

Q0–Q17

RDCLK

RDEN

OR

Q18–Q35

OE

WRTCLK

WRTEN

D18–D35

IR

D0–D17

SN74ACT7882

WRTCLK

WRTEN1

WRTEN2

IR

D0–D17

RDCLK

RDEN1

RDEN2

OR

OE

Q0–Q17

Q0–Q17

Figure 9. Word-Width Expansion: 2048

× 36 Bits