SN74ALVC00

QUADRUPLE 2-INPUT POSITIVE-NAND GATE

SCES115C – JULY 1997 – REVISED AUGUST 1998

1

POST OFFICE BOX 655303

CMOS) Submicron Process

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

JESD 17

Small-Outline (D), Thin Very Small-Outline

(DGV), and Thin Shrink Small-Outline (PW)

Packages

description

The SN74ALVC00 performs the Boolean function Y = A

• B or Y = A + B in positive logic.

The SN74ALVC00 is characterized for operation from –40

°C to 85°C.

FUNCTION TABLE

(each gate)

INPUTS

OUTPUT

A

B

Y

H

H

L

L

XH

X

L

H

1

1A

2

1B

1Y

3

4

2A

5

2B

2Y

6

9

3A

10

3B

3Y

8

12

4A

13

4B

4Y

11

&

† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

logic diagram, each gate (positive logic)

A

B

Y

Copyright

© 1998, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments Incorporated.

D, DGV, OR PW PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

14

13

12

11

10

9

8

1A

1B

1Y

2A

2B

2Y

GND

4B

4A

4Y

3B

3A

3Y