SN74ALVC7803 datasheet(1/14 Pages) TI

Part #	SN74ALVC7803

Description	512 횞 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY

PDF	14 Pages

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Manufacturer	TI [Texas Instruments]

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SN74ALVC7803

512

× 18

CLOCKED FIRST-IN, FIRST-OUT MEMORY

SDAS274 – JANUARY 1995

Copyright

1

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

• Operates at 3-V to 3.6-V V

CC

• Free-Running Read and Write Clocks Can

Be Asynchronous or Coincident

• Read and Write Operations Synchronized to

Independent System Clocks

• Low-Power Advanced CMOS Technology

• Half-Full Flag and Programmable

Almost-Full/Almost-Empty Flag

• Bidirectional Configuration and Width

Expansion Without Additional Logic

• Input-Ready Flag Synchronized to Write

Clock

• Output-Ready Flag Synchronized to Read

Clock

• Fast Access Times of 13 ns With a 50-pF

Load and All Data Outputs Switching

Simultaneously

• Data Rates From 0 to 50 MHz

• Pin Compatible With SN74ACT7803

• Packaged in Shrink Small-Outline 300-mil

Package (DL) Using 25-mil Center-to-Center

Lead Spacing

description

The SN74ALVC7803 FIFO is suited for buffering

asynchronous data paths at 50-MHz clock rates

and 13-ns access times and is designed for 3-V to

3.6-V VCC operation. The 56-pin shrink small-

outline (DL) package offers greatly reduced board

space over DIP, PLCC, and conventional SOIC

packages. Two devices can be configured for

bidirectional data buffering without additional

logic.

The write clock (WRTCLK) and read clock (RDCLK) should be free running and can be asynchronous or

coincident. Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, WRTEN2 is low,

and input ready (IR) is high. Data is read from memory on the rising edge of RDCLK when RDEN, OE1, and

OE2 are low and output ready (OR) is high. The first word written to memory is clocked through to the output

buffer regardless of the RDEN, OE1, and OE2 levels. The OR flag indicates that valid data is present on the

output buffer.

The FIFO can be reset asynchronously to WRTCLK and RDCLK. RESET must be asserted while at least four

WRTCLK and four RDCLK rising edges occur to clear the synchronizing registers. Resetting the FIFO initializes

the IR, OR, and half-full (HF) flags low and the almost-full /almost-empty (AF/AE) flag high. The FIFO must be

reset upon power up.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

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RESET

D17

D16

D15

D14

D13

D12

D11

D10

VCC

D9

D8

GND

D7

D6

D5

D4

D3

D2

D1

D0

HF

PEN

AF/AE

WRTCLK

WRTEN2

WRTEN1

IR

OE1

Q17

Q16

Q15

GND

Q14

VCC

Q13

Q12

Q11

Q10

Q9

GND

Q8

Q7

Q6

Q5

VCC

Q4

Q3

Q2

GND

Q1

Q0

RDCLK

RDEN

OE2

OR

DL PACKAGE

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