TLC1549C, TLC1549I, TLC1549M

10-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL

SLAS059C – DECEMBER 1992 – REVISED MARCH 1995

12

POST OFFICE BOX 655303

Sample Cycle B

A/D Conversion

Interval

(

≤ 21 µs)

Initialize

MSB

LSB

Previous Conversion Data

B9

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

Low Level

1

2

3

4

567

8

9

10

1

I/O

CLOCK

DATA

OUT

CS

Initialize

Must Be High on Power Up

14

15

16

See Note C

(see Note A)

Figure 9. Timing for 16-Clock Transfer Not Using CS (Serial Transfer Completed Within 21

µs)

Sample Cycle B

Conversion

Interval

Initialize

MSB

LSB

Previous Conversion Data

B9

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

12

3

4

5

6

7

8

9

10

1

I/O

CLOCK

DATA

OUT

CS

Initialize

11

Hi-Z State

16

Low

Level

(see Note A)

(

≤ 21 µs)

A/D

See Note B

Figure 10. Timing for 11- to 16-Clock Transfer Using CS (Serial Transfer Completed After 21

µs)

Sample Cycle B

A/D Conversion Interval

Initialize

MSB

LSB

Previous Conversion Data

B9

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

12

3

4

5

6

7

8

9

10

1

I/O

CLOCK

DATA

OUT

CS

Must Be High on Power Up

14

15

16

See Note C

See Note B

Low Level

(see Note A)

(

≤ 21 µs)

Figure 11. Timing for 16-Clock Transfer Not Using CS (Serial Transfer Completed After 21

µs)

NOTES: A. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system

clock after CS

↓ before responding to the I/O CLOCK. No attempt should be made to clock out the data until the minimum CS setup

time has elapsed.

B. A low-to-high transition of CS disables I/O CLOCK within a maximum of a setup time plus two falling edges of the internal system

clock.

C. The first I/O CLOCK must occur after the end of the previous conversion.